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256k x 16 static ram cy62146cv18 mobl2 ? cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05010 rev. *b revised october 31, 2001 features high speed ? 55 ns and 70 ns availability low voltage range: ? cy62146cv18: 1.65v ? 1.95v pin compatible w/ cy62146v18/bv18 ultra-low active power ? typical active current: 0.5 ma @ f = 1 mhz ? typical active current: 2 ma @ f = f max (70 ns speed) low standby power easy memory expansion with ce and oe features automatic power-down when deselected cmos for optimum speed/power functional description the cy62146cv18 is a high-performance cmos static ram organized as 256k words by 16 bits. this device features ad- vanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. the device can also be put into standby mode when deselect- ed (ce high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high en- able and byte low enable are disabled (bhe , ble high), or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip en- able (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete de- scription of read and write modes. the cy62146cv18 is available in 48-ball fbga packaging. mobl, mobl2, and more battery life are trademarks of cypress semiconductor corporation. logic block diagram 256k x 16 ram array i/o 0 ? i/o 7 column decoder a 11 a 12 a 13 a 14 a 15 2048 x 2048 sense amps data in drivers oe i/o 8 ? i/o 15 ce we ble bhe a 16 row decoder a 7 a 6 a 3 a 0 a 2 a 1 a 5 a 4 a 8 a 9 a 10 a 17
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 2 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage to ground potential .................? 0.2v to +2.4v dc voltage applied to outputs in high z state [3] ....................................... ? 0.2v to v cc + 0.2v dc input voltage [3] .................................... ? 0.2v to v cc + 0.2v output current into outputs (low)............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma notes: 1. nc pins are not connected to the die. 2. e3 (dnu) can be left as nc or v ss to ensure proper application. 3. v il (min) = ? 2.0v for pulse durations less than 20 ns. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. pin configuration [1, 2] we v ccq a 11 a 10 a 17 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ssq a 7 i/o 0 bhe nc dnu a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h fbga a 16 top view operating range device range ambient temperature v cc cy62146cv18 industrial ? 40 c to +85 c 1.65v to 1.95v product portfolio product v cc range speed power dissipation (industrial) operating (i cc ) standby (i sb2 ) f = 1 mhz f = f max v cc(min) v cc(typ) [4] v cc(max) typ. [4] max. typ. [4] max. typ. [4] max. cy62146cv18 1.65v 1.80v 1.95v 55 ns 0.5 ma 3 ma 2.5 ma 7 ma 1 a10 a 70 ns 0.5 ma 3 ma 2 ma 6 ma
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 3 of 12 electrical characteristics over the operating range test conditions cy62146cv18-55 cy62146cv18-70 parameter description min. typ. [4] max. min. typ. [4] max. unit v oh output high voltage i oh = ?0 .1 ma v cc = 1.65v 1.4 1.4 v v ol output low voltage i ol = 0.1 ma v cc = 1.65v 0.2 0.2 v v ih input high voltage 1.4 v cc + 0.2v 1.4 v cc + 0.2v v v il input low voltage ? 0.2 0.4 ? 0.2 0.4 v i ix input leakage current gnd < v i < v cc ? 1+1 ? 1+1 a i oz output leakage current gnd < v o < v cc , output dis- abled ? 1+1 ? 1+1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 1.95v i out = 0 ma cmos levels 2.5 7 2 6 ma f = 1 mhz 0.5 3 0.5 3 ma i sb1 automatic ce power-down cur- rent ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v, v in < 0.2v f = f max (address and data only), f = 0 (oe , we , bhe , and ble ) 110 110 a i sb2 automatic ce power-down cur- rent ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 1.95v capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 6 pf c out output capacitance 8 pf thermal resistance description test conditions symbol bga unit thermal resistance (junction to ambient) [5] still air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ja 55 c/w thermal resistance (junction to case) [5] jc 16 c/w note: 5. tested initially and after any design or process changes that may affect these parameters.
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 4 of 12 note: 6. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. ac test loads and waveforms v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v equivalent to: th venin equivalent all input pulses rth r1 rise time: 1 v/ns fall time: 1 v/ns parameters 1.8v unit r1 13500 ohms r2 10800 ohms r th 6000 ohms v th 0.80 volts data retention characteristics (over the operating range) parameter description conditions min. typ. [4] max. unit v dr v cc for data retention 1.0 1.95 v i ccdr data retention current v cc = 1.0v ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 1 8 a t cdr [5] chip deselect to data retention time 0 ns t r [6] operation recovery time t rc ns data retention waveform v cc(min.) v cc(min.) t cdr v dr > 1.0 v data retention mode t r ce v cc
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 5 of 12 switching characteristics over the operating range [7] 55 ns 70 ns parameter description min. max. min. max. unit read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [8] 5 5 ns t hzoe oe high to high z [8, 9] 20 25 ns t lzce ce low to low z [8] 5 10 ns t hzce ce high to high z [8, 9] 20 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 55 70 ns t dbe ble /bhe low to data valid 25 35 ns t lzbe ble /bhe low to low z [8] 5 5 ns t hzbe ble /bhe high to high z [8, 9] 20 25 ns write cycle [10] t wc write cycle time 55 70 ns t sce ce low to write end 40 60 ns t aw address set-up to write end 40 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 50 ns t bw ble /bhe low to write end 40 60 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [8, 9] 15 25 ns t lzwe we high to low z [8] 5 10 ns notes: 7. test conditions assume signal transition time of 3ns or less, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh and 30-pf load capacitance 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe, t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzce , t hzbe and t hzwe transitions are measured when the outputs enter a high impedance state. 10. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble =v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write.
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 6 of 12 switching waveforms notes: 11. device is continuously selected. oe , ce = v il , bhe and/or ble = v il. . 12. we is high for read cycle. 13. address valid prior to or coincident with ce , bhe , ble , transition low. address data out previous data valid data valid t rc t aa t oha read cycle no. 1(address transition controlled) [11, 12] read cycle no. 2 (oe controlled) [12, 13] 50% 50% data valid t rc t ace t dbe t lzbe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hzbe bhe /ble t lzoe address t doe
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 7 of 12 notes: 14. data i/o is high impedance if oe = v ih . 15. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 16. during this period, the i/os are in output state and input signals should not be applied. switching waveforms t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 16 write cycle no. 1(we controlled) bhe /ble t bw [10, 14, 15] t hd t sd t pwe t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 16 write cycle no. 2 (ce controlled) bhe /ble t bw [10, 14, 15] t sa
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 8 of 12 switching waveforms data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 16 write cycle no. 3 (we controlled, oe low) t bw bhe /ble [15] data i/o address t hd t sd t sa t ha t aw t wc ce 1 we data in valid write cycle no. 4 (bhe /ble controlled, oe low) [15] note 16 t bw bhe /ble t sce t pwe
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 9 of 12 typical dc and ac characteristics ( typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc typ, t a = 25 c.) truth table ce we oe bhe ble inputs/outputs mode power h x x x x high z deselect/power-down standby (i sb ) l x x h h high z output disabled active (i cc ) l h l l l data out (i/o o ? i/o 15 ) read active (i cc ) l h l h l data out (i/o o ? i/o 7 ); i/o 8 ? i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ? i/o 15 ); i/o 0 ? i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o o ? i/o 15 ) write active (i cc ) l l x h l data in (i/o o ? i/o 7 ); i/o 8 ? i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ? i/o 15 ); i/o 0 ? i/o 7 in high z write active (i cc ) 3.5 3.0 1.5 1.0 0.5 1.80 0 2.0 i sb ( a) 2.4 2.0 1.2 0.8 0.4 1.65 1.80 1.95 0.0 1.6 i cc (ma) 40 35 25 20 15 1.65 1.8 1.95 supply voltage (v) access time vs. supply voltage 10 30 t aa (ns) operating current standby current vs. supply voltage supply voltage (v) supply voltage (v) mobl2 mobl2 mobl2 vs. supply voltage 1.95 1.65 (f = f max , 55 ns) (f = f max , 70 ns) (f = 1 mhz)
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 10 of 12 ordering information [17] speed (ns) ordering code package name package type operating range 70 CY62146CV18LL-70BAI ba48b 48-ball fine pitch bga (7mm x 8.5mm x 1.2mm) industrial cy62146cv18ll-70bvi bv48a 48-ball fine pitch bga (6mm x 8mm x 1mm) 55 cy62146cv18ll-55bai ba48b 48-ball fine pitch bga (7mm x 8.5mm x 1.2mm) cy62146cv18ll-55bvi bv48a 48-ball fine pitch bga (6mm x 8mm x 1mm) package diagrams note: 17. gray shading represents preliminary information. 48-ball (7 mm x 8.5 mm x 1.2 mm) fine pitch bga ba48b 51-85106-b
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 11 of 12 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 48-ball (6 mm x 8 mm x 1 mm) fine pitch bga bv48a to p v i e w bottom view prel i minary
cy62146cv18 mobl2 ? document #: 38-05010 rev. *b page 12 of 12 document title: cy62146cv18 mobl2 ? , 256k x 16 static ram document number: 38-05072 rev. ecn no. issue date orig. of change description of change ** 107265 09/15001 szv change from spec number: 38-01046 to 38-05072 *a 107702 06/15/01 mgn deactivated spec. *b 111468 11/02/01 mgn die rev (r5 to r7), change part number from cy62146bv18 to cy62146cv18

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